This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-070988, filed on Mar. 14, 2002, the entire contents of which are incorporated herein by reference.
The present invention relates to an asynchronous semiconductor memory device, and more particularly, to the stabilization of data output from an asynchronous semiconductor memory device during high frequency operation.
A flash memory, which is a non-volatile semiconductor memory that enables electrical writing and erasing of data, is used in a portable information terminal, such as a cellular phone. Due to the recent increase in the speed for transmitting and receiving data, the cycle time of a flash memory (i.e., the time from when data is output to the time when data is subsequently output) has been shortened. This has shortened the margin of the time for validating the output of data. The shortened margin results in reading errors. It is thus desired that the occurrence of such reading errors be prevented.
A flash memory is in synchronism with a system clock signal CLK. In the flash memory, the read data output is controlled by a read enable signal REB/ (read enable bar: negative logic). For example, when the duty ratio (the ratio between a high level and a low level) of the read enable signal REB is 50%, the output valid time of the read data is about half of that of the read cycle time.
FIG. 1 is a timing chart illustrating an example of high impedance or disconnecting control (hereafter, referred to as Hi-Z control) in an asynchronous memory. During the Hi-Z control, an output terminal of the memory device is in a disconnected state (Hi-Z state) for an external device.
In response to a trailing edge of the read enable signal REB at time t1, an I/O terminal exits the Hi-Z state. At time t2, read data DQ1 is output. In response to a rising edge of the read enable signal REB at time t3, the I/O terminal is controlled in the Hi-Z state. At time t4, output is disabled.
Accordingly, when the duty ratio of the read enable signal is about 50%, the output valid time of the read data DQ1 (i.e., the period between time t2 to t4) is about half the read cycle time (i.e., the period between time t1 to t5). Read data DQ2 and DQ3 are also output in the same manner as the read data DQ1. When a plurality of memory devices use the same I/O bus (data input and output bus), such Hi-Z control is performed to prevent the occurrence of bus competition (bus fight) between memory devices.
The increase in the speed of the entire memory system (i.e., shifting to higher frequency) due to the high occupying rate of the I/O bus shortens the read cycle time. The shortened read cycle time reduces the margin of the data output valid time. That is, when the cycle time (time t1 to t5) is shortened, it becomes difficult to guarantee the output valid time of the read data DQ1 to DQ3. Thus, the retrieval of the read data DQ1 to DQ3 by the memory controller cannot be guaranteed.
An extended data out (EDO) technique (hyper page mode), which holds the immediately previous data until the next data is provided, has been proposed to solve this problem. FIG. 2 is a schematic block diagram of a prior art extended data out DRAM system (hereinafter, referred to as EDO-DRAM) 60. The DRAM system 60 includes an asynchronous semiconductor device (hereinafter, referred to as memory device) 61 and a memory controller 62, such as a CPU, for controlling the memory device 61.
In response to a trailing edge of the read enable signal REB from the memory controller 62, the memory device 61 provides the memory controller 62 with an I/O signal DQ, which is read data. The I/O signal DQ (read data) is held until the memory device 61 is provided with the next read enable signal REB (trailing edge). The output terminal of the memory device 61 is controlled in a Hi-Z state by the I/O control signal OEB/ (output enable bar: negative logic) from the memory controller 62.
FIG. 3 is a timing chart illustrating the Hi-Z control of the EDO-DRAM system 60. When an I/O control signal OEB is output at a low level, the I/O terminal exits the Hi-Z state in response to the trailing edge of the read enable signal REB at time t1. Read data DQ11 is output at time t2. In response to the trailing edge of the read enable signal REB at time t3, the read data DQ11 is held until the output of the next read data DQ12 starts at time t4. In the same manner, in response to the trailing edge of the read enable signal REB at time t5, the read data DQ12 is held until the output of the next read data DQ13 starts at time t6. After the read data DQ13 is output, the I/O terminal is controlled in a Hi-Z state in response to the rising edge of the I/O control signal OEB at time t7. At time t8, the read output is disabled.
In the EDO-DRAM system 60, the read data DQ11 to DQ13 is output substantially during the read cycle time (time t1 to t3). Accordingly, the output valid time of the read data DQ11 to DQ13 is guaranteed even if the increase in the speed of the memory system (i.e., shifting to high frequency) shortens the cycle time.
To cope with the demand for memories having higher capacities and lower power consumption, NAND flash memories are now used in portable information terminals, such as cellular phones. However, when employing the EDO technique for a NAND flash memory, to use the I/O control signal OEB for Hi-Z control, an exclusive terminal for the I/O control signal OEB becomes necessary. Such addition of the Hi-Z control exclusive terminal increases the number of internal control circuits in the memory device and increases the circuit area of the memory. Further, the number of control signals used by the memory controller and the memory system increases. This affects the other user circuits laid out on the same semiconductor substrate. The Hi-Z control exclusive terminal is necessary for the following reason.
The EDO technique is also applied to a synchronous memory system, such as a SDRAM. In a synchronous memory system, the Hi-Z control is performed in synchronism with a system clock signal. Accordingly, a Hi-Z control exclusive terminal is not necessary in the synchronous memory system. An SDRAM employing the EDO technique will now be discussed.
FIG. 4 is a schematic block diagram of an SDRAM 70. The SDRAM system 70 includes a synchronous semiconductor memory device 71 and a memory controller 72, such as a CPU, for controlling the memory device 71. The memory controller 72 provides the memory device 71 with a system clock signal CLK and a command control signal CMD. When the memory device 71 receives the command control signal CMD (read command) from the memory controller 72, the memory device 71 outputs an I/O signal DQ (read data) having a predetermined burst length in response to (in synchronism with) the system clock signal CLK.
For example, when the burst length corresponds to a full page, the memory device 71 sets the output terminal in the Hi-Z state in response to the rising edge of the next system clock signal CLK in accordance with a burst stop command (not shown) from the memory controller 72. Then, the memory device 71 completes the burst operation. When the burst length corresponds to pages other than the full page (e.g., 1, 2, 4, 8), an internal counter of the memory device 71 counts the number of bursts. After completing the burst operation, the memory device 71 sets the output terminal in a Hi-Z state in response to the rising edge of the next system clock signal CLK.
FIG. 5 is a timing chart illustrating an example of the Hi-Z control of the SDRAM when the burst length is xe2x80x9c2xe2x80x9d. After the read command is provided, the I/O terminal exits the Hi-Z state of the I/O terminal after time tLZ elapses from when the system clock signal CLK goes high at time t1. Then, the output of the read data is held until time tOH elapses from when the system clock signal CLK goes high at time t2 (the output valid time is determined). The output of the read data is held until time tOH elapses from when the system clock signal CLK goes high at time t3. The I/O terminal enters the Hi-Z state after time tHZ elapses from time t3.
In the synchronous memory system, the Hi-Z state ends in response to the rising edge of the system clock signal CLK when the burst operation is started. Further, the Hi-Z control begins in response to the rising edge of the next system clock signal CLK after the burst operation ends. Accordingly, for an n number of burst operations, an (n+1) number of system clock signals CLK is used.
An synchronous memory device employing the EDO technique does not have an input terminal for the system clock signal CLK but has an input terminal for a control chip enable signal (not shown). The chip enable signal cannot be used for the Hi-Z control due to the following reason. The chip enable signal is generated by a memory controller. When data is received from a memory device, the chip enable signal goes high once and goes low only once. Accordingly, in the asynchronous memory, two chip enable signals cannot be generated for a single burst operation like in the synchronous memory. Thus, in an asynchronous memory system employing the EDO technique, an additional exclusive terminal for the I/O control signal OEB is necessary to perform the Hi-Z control.
One aspect of the present invention is an asynchronous semiconductor memory device including a memory unit, an output circuit for outputting data read from the memory unit, and an output control circuit connected to the output circuit for storing read completion information and comparing present read operation information with the read completion information. The output control circuit causes the output circuit to enter a disconnected state when the present read operation information substantially coincides with the read completion information.
A further aspect of the present invention is a method for controlling an output circuit that outputs data read from a memory unit of an asynchronous semiconductor memory. The method includes storing read completion information, comparing present read operation information with the read completion information, and causing the output circuit to enter a disconnected state when the present read operation information substantially coincides with the read completion information.
A further aspect of the present invention is a memory system including an asynchronous semiconductor memory device and a controller for controlling the semiconductor memory device. The controller provides data read completion information of data to the semiconductor memory device. The semiconductor memory device includes a memory unit, an output circuit for outputting data read from the memory unit, and an output control circuit connected to the output circuit for storing read completion information and comparing present read operation information with the read completion information. The output control circuit causes the output circuit to enter a disconnected state when the present read operation information substantially coincides with the read completion information.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.